This invention relates to telecommunication systems and more particularly to methods and apparatus requiring less memory in radio systems, such as a wideband code division multiple access (WCDMA) system.
Digital communication systems include time-division multiple access (TDMA) systems, such as cellular radio telephone systems that comply with the GSM telecommunication standard and its enhancements like GSM/EDGE, and code-division multiple access (CDMA) systems, such as cellular radio telephone systems that comply with the IS-95, cdma2000, and WCDMA telecommunication standards. Digital communication systems also include “blended” TDMA and CDMA systems, such as cellular radio telephone systems that comply with the universal mobile telecommunications system (UMTS) standard, which specifies a third generation (3G) mobile system being developed by the European Telecommunications Standards Institute (ETSI) within the International Telecommunication Union's (ITU's) IMT-2000 framework. The Third Generation Partnership Project (3GPP) promulgates the UMTS standard. This application focusses on WCDMA systems for simplicity, but it will be understood that the principles described in this application can be implemented in other digital communication systems.
FIG. 1 depicts a communication system such as a WCDMA system that includes a base station (BS) 10 handling connections with four mobile stations (MSs) 1, 2, 3, 4 that each use downlink (i.e., base-to-mobile or forward) and uplink (i.e., mobile-to-base or reverse) channels. In the downlink, BS 10 transmits to each mobile at a respective power level, and the signals transmitted by BS 10 are spread using orthogonal code words. In the uplink, MS 1-MS 4 transmit to BS 10 at respective power levels. Although not shown, BS 10 also communicates with a radio network controller (RNC), which in turn communicates with a public switched telephone network (PSTN).
WCDMA is based on direct-sequence spread-spectrum techniques. Two different codes are used for separating base stations and physical channels in the downlink (base-to-terminal) direction. Scrambling codes are pseudo-noise (pn) sequences that are mainly used for separating the base stations or cells from each other. Channelization codes are orthogonal sequences that are used for separating different physical channels (terminals or users) in each cell or under each scrambling code. User terminals communicate with the system through, for example, respective dedicated physical channels (DPCHs). It will be appreciated that WCDMA terminology is used here and that other systems have corresponding terminology. Scrambling and channelization codes are well known in the art.
The signals transmitted in the exemplary WCDMA system depicted in FIG. 1 can be formed with a transmitter system 100 such as that depicted in FIG. 2. An information data stream to be transmitted, such as a serial stream of bits to be sent on a downlink physical channel, is converted from serial form to parallel form by a suitable converter 102, and the now-parallel bits to be sent are provided to a modulation mapper 104 that transforms groups of bits into respective modulation symbols. WCDMA and other transmitters employ quadrature modulation, so the mapper 104 generates streams of in-phase (I) and quadrature (Q) symbols that are provided to respective multipliers 106, 108 that combine the symbols with a selected channelization code. As shown in FIG. 2, the resultant streams are provided to a combiner 110, and then the resultant combined stream is provided to another multiplier 112 that combines the combined stream with a selected scrambling code. The resultant channelized, scrambled signal may then be further processed and impressed on a suitable carrier signal (not shown) for transmission.
The multiplications are usually carried out by exclusive-OR operations, and the information data stream and the scrambling code can have the same or different bit rates. Each information data stream or channel is allocated a unique channelization code, and a plurality of coded information signals simultaneously modulate a radio-frequency carrier signal.
In order to accommodate the increasing demand for higher data rates in wireless user equipment (UE), such as cellular telephones, combination cellular telephones-personal digital assistants, and wireless-enabled personal computers, a high-speed downlink shared channel (HS-DSCH) was introduced in WCDMA. The HS-DSCH has a spreading factor of sixteen and can use several channelization codes simultaneously, with modulation being either quadrature phase shift keying (QPSK) or 16-ary quadrature amplitude modulation (16QAM). Each transmission time interval (TTI) includes one transport block, and the length of a TTI is three slots. After encoding, interleaving, and rate matching, the bits to be transmitted are distributed over one or more channelization codes. This is described in “Multiplexing and channel coding (FDD)”, 3GPP Technical Specification (TS) 25.212 ver. 5.6.0 (September 2003), for example. Since the chip rate in a direct-sequence CDMA system is typically constant, a higher spreading factor generally corresponds to a lower information bit-rate.
The transmitter 100 depicted in FIG. 2 is suitable for the HS-DSCH, and the 16QAM symbol constellation generated by the modulation mapper 104 is depicted in FIG. 3. The region marked i1 is where the first bit is mapped when it is one; the region marked q1 is where the second bit is mapped when it is one; the region marked i2 is where the third bit is mapped when it is one; and the region marked q2 is where the fourth bit is mapped when it is one. It should be noted that input binary zeroes are mapped to ones and input binary ones are mapped to negative ones.
At a mobile station or other receiver, the modulated carrier signal is processed to produce an estimate of the original information data stream intended for the receiver. This process is known as demodulation. The composite received baseband spread signal is commonly provided to a rake processor that includes a number of “fingers”, or de-spreaders, that are each assigned to respective ones of selected components, such as multipath echoes or images, in the received signal. Each finger combines a received component with the scrambling sequence and the channelization code so as to de-spread the received composite signal. The rake processor typically de-spreads both sent information data and pilot or training symbols that are included in the composite signal.
Various aspects of rake receivers are described in G. Turin, “Introduction to Spread-Spectrum Antimultipath Techniques and Their Application to Urban Digital Radio”, Proc. IEEE, vol. 68, pp. 328-353 (March 1980); U.S. Pat. No. 5,305,349 to Dent for “Quantized Coherent Rake Receiver”; U.S. Patent Application Publication No. 2001/0028677 by Wang et al. for “Apparatus and Methods for Finger Delay Selection in Rake Receivers”; and U.S. Patent Applications No. 09/165,647 filed on Oct. 2, 1998, by G. Bottomley for “Method and Apparatus for Interference Cancellation in a Rake Receiver” and No. 09/344,898 filed on Jun. 25, 1999, by Wang et al. for “Multi-Stage Rake Combining Methods and Apparatus”.
FIG. 4 is a block diagram of a typical HS-DSCH receiver 400. A rake processor 402 receives over-sampled chip values from one or more analog-to-digital converters (not shown). The rake processor 402 sub-samples the received over-sampled chip sequence and multiplies each chip with the corresponding scrambling and channelization codes. The first chip to select is determined by the appropriate multi-path delay, and these delays are determined by a suitable path estimator 404. The output of the rake processor is a set of symbols corresponding to different channelization codes and multi-path delays. It will be understood that FIG. 4 omits any components that might be used for recovering the baseband modulation of a radio-frequency carrier signal.
A combiner 406 multiplies the symbols for each delay with the complex conjugate of an estimate of the impulse response of the propagation channel for the corresponding delay and sums the contributions over the delays. The channel estimates are produced by a suitable channel estimator 408. The combiner 406 thus reproduces the modulated complex symbols that were transmitted. Not shown in FIG. 4 are various registers or memories that are usually used in practice to enable received signals to be processed while new signals are received. For example, a memory is placed before the rake processor 402 for so-called over-sampled chip buffering or after the rake processor for so-called symbol buffering.
When receiving 16QAM-modulated symbols, the constellation of which is depicted in FIG. 3, the receiver has to determine the distance d between the Q-axis and the point on the I-axis that is half-way between the first and second columns of constellation points in the right half-plane in order to decide which symbols have been received. As depicted in FIG. 3, the first column of points is located at 0.4472 on the I-axis and the second column of points is located at 1.3416, so the distance d is 0.8944. Because of the symmetry of the constellation, the determined distance d separates all of the constellation points into a uniform pattern of squares.
The distance d is proportional to the amplitude of the received signal, and that amplitude varies with time due to signal fading in the propagation channel. Thus, when the receiver is in a fading dip, the distance d is small, and when the receiver is on a fading peak, the distance d is large. Accordingly, the receiver must regularly update its determination of the distance d. FIG. 4 shows a memory 410 after the combiner 406 that stores a number of complex symbols generated by the combiner. A decision boundary estimator 412 computes the distance d separately for each channelization code based on respective symbols in the memory 410 and on respective previously computed values of the distance d for each channelization code. Using the estimates of the distance d computed by the estimator 412, a soft bit value estimator 414 computes so-called soft bit values from the complex symbols stored in the memory 410.
The computed soft bit values may be stored in a memory called a Hybrid ARQ (HARQ) buffer that implements hybrid automatic repeat request (HARQ). HARQ is a combination (a hybrid) of ARQ and forward error correction coding (FEC), which are well known techniques for increasing the probability of successful signal reception in the face of channel noise and interference from other users. Another known error handling technique is interleaving, in which symbols are interleaved, or shuffled out of order, at the transmitter and correspondingly deinterleaved, or re-ordered, at the receiver. HARQ, interleaving, and the HS-DSCH are described in, for example, the 3GPP TS 25.212 ver. 5.6.0 (September 2003) standard cited above.
FIG. 4 depicts the HARQ and deinterleaving functionality in a combined deinterleaver/HARQ buffer 416. The computed soft bit values are not removed from the HARQ buffer 416 until the transmitted transport block has been decoded correctly by a suitable decoder 418 or when higher signalling layers inform the HARQ buffer to clear the soft bit values. Multiple retransmissions may occur for a given block until it has been decoded correctly. The soft bit values from each retransmission are combined and stored in the HARQ buffer 416. The transmitter, such as a cellular base station, is eventually informed, for example via an uplink high-speed dedicated physical control channel (HS-DPCCH), that the block has been received correctly.
Having the memory 410 between the combiner 406 and the decision boundary estimator 412 as in FIG. 4 is costly in several ways. For example, the memory size must be on the order of five kilobits (5 kbits), and this requires a corresponding area on one of the integrated circuit (IC) chips used for the receiver 400. The chip die area could be reduced if the memory 410 could be eliminated.